publications

2026

1. DAC

   Stochastic Diffusion Prior: Knowledge Elicitation and Local Adaptation for Transistor Sizing

   Wei W. Xing^*, Zhuohua Liu^*, Weilun Xie, Yuxuan Zhang, Yuan Yao, and Yuanqi Hu

   In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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   Proposed a stochastic diffusion prior framework for knowledge elicitation and local adaptation in transistor sizing, combining generative modeling with Bayesian optimization.

2. DAC

   Exploiting Function-Family Structure in Analog Circuit Optimization

   Zhuohua Liu, Kaiqi Huang, Qinxin Mei, Yuanqi Hu, and Wei W. Xing

   In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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   Exploits function-family structural constraints in analog circuit optimization using TabPFN v2 with Direct Expected Improvement, achieving significantly better results than GP surrogates in small-sample regimes.

3. DAC

   OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM

   Yiqi Zhou, Yue Yuan, Yikai Wang, Bohao Liu, Qinxin Mei, Zhuohua Liu, Shan Shen, Wei Xing, Daying Sun, Li Li, and Guozhu Liu

   In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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   An accuracy-constrained co-optimization framework for approximate digital computing-in-memory (DCiM) designs.

4. ASP-DAC

   Phi-BO: Physics-Informed Bayesian Optimization for Multi-Port Decoupling Capacitor Placement in 2.5-D Chiplets

   Quansen Wang^*, Yuchuan Lin^*, Zhuohua Liu, Wei Xing, Wei Zhang, Ning Xu, and Yuanqing Cheng

   In 2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026

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   Proposed a physics-informed Bayesian optimization framework for multi-port decoupling capacitor placement in 2.5-D chiplet designs.

5. ASP-DAC

   Automated Parameter Tuning for Multi-FPGA Partitioning: A Preference-Guided Approach

   Yutao Dai^*, Shengbo Tong^*, Chunyan Pei, Zhuohua Liu, Wei Xing, Yi Liu, Rui Wang, and Wenjian Yu

   In 2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026

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   A preference-guided approach for automated parameter tuning in multi-FPGA partitioning workflows.

2025

1. ICCAD

   DIVE: Dynamic Information-Guided Variable Expansion for Deeper Analog Circuit Optimization

   Zhuohua Liu, Weilun Xie, Yuxuan Zhang, Chen Wang, Yuanqi Hu, and Wei W. Xing

   In 2025 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

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   Proposed DIVE, a dynamic information-guided variable expansion framework that tackles the dimensionality challenge in analog circuit optimization, achieving up to 21.11x simulation reduction and 2.69x performance improvement.

2. ICCAD

   ASTRA: Automatic Sizing of Transistors with Reasoning Agents

   Wei W. Xing, Baowen Ou, Yuxuan Zhang, Zhuohua Liu, and Yuanqi Hu

   In 2025 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

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   Proposed ASTRA, an automatic transistor sizing framework leveraging LLM-based reasoning agents integrated with Bayesian Optimization for efficient analog circuit design.

3. ICCD

   OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite

   Shan Shen^*, Xingyang Li^*, Zhuohua Liu^*, Junhao Ma, Yikai Wang, Yiheng Wu, Yuquan Sun, and Wei W. Xing

   In 2025 IEEE 43rd International Conference on Computer Design (ICCD), 2025

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   Best Paper Candidate

   Built a realistic SRAM yield analysis and optimization benchmark integrating parasitic-aware circuit generation and baseline evaluation frameworks.

4. ISEDA

   Design Space Folding: A Free-lunch Add-on for Efficient Design Convergence in Transistor Sizing

   Zhuohua Liu, Yuxuan Zhang, Weilun Xie, Yuanqi Hu, and Wei W. Xing

   In 2025 International Symposium of Electronics Design Automation (ISEDA), 2025

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   Developed a framework that enhances existing Bayesian optimization methods for transistor sizing, reducing simulation cost by up to 50 percent and improving design performance by up to 50 percent.

2024

1. DAC

   KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology

   Wei W. Xing, Weijian Fan, Zhuohua Liu, Yuan Yao, and Yuanqi Hu

   In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

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   Proposed an efficient and generalizable knowledge alignment and transfer framework for analog transistor sizing, reducing simulation cost by up to 50 percent and improving design performance by up to 20 percent.