Zhuohua Liu

School of Integrated Circuits Science and Engineering

Beihang University, Beijing, China

zhuohualiu@buaa.edu.cn

I am a Ph.D. candidate at the School of Integrated Circuits Science and Engineering, Beihang University, advised by Prof. Yuanqi Hu (Sept 2025, expected graduation 2030). My research focuses on AI for EDA, with particular interests in analog circuit optimization, transistor sizing, and Bayesian optimization.

I received my Bachelor of Engineering from the School of Mechanical, Electrical and Control Engineering, Shenzhen University (Sept 2021 – Jul 2025)

My research has been published at top EDA venues including DAC (CCF-A), ICCAD (CCF-B), and ICCD (CCF-B, Best Paper Candidate). I am committed to developing efficient, generalizable optimization frameworks that bridge machine learning and circuit design automation.

news

Feb 23, 2026	🎉 Three papers accepted to DAC 2026 (CCF-A)!
Nov 30, 2025	🏆 Won 1st Prize (National Final) at the 2025 China Postgraduate IC Innovation Competition — EDA Elite Challenge Contest!
Sep 05, 2025	🎉 Two papers accepted to ASP-DAC 2026 (CCF-C)!
Aug 01, 2025	🎉 One paper accepted to ICCD 2025 (CCF-B) as Best Paper Candidate!
Jun 30, 2025	🎉 Two papers accepted to ICCAD 2025 (CCF-B)!

selected publications

DAC

Stochastic Diffusion Prior: Knowledge Elicitation and Local Adaptation for Transistor Sizing

Wei W. Xing^*, Zhuohua Liu^*, Weilun Xie, Yuxuan Zhang, Yuan Yao, and Yuanqi Hu

In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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Proposed a stochastic diffusion prior framework for knowledge elicitation and local adaptation in transistor sizing, combining generative modeling with Bayesian optimization.
DAC

Exploiting Function-Family Structure in Analog Circuit Optimization

Zhuohua Liu, Kaiqi Huang, Qinxin Mei, Yuanqi Hu, and Wei W. Xing

In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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Exploits function-family structural constraints in analog circuit optimization using TabPFN v2 with Direct Expected Improvement, achieving significantly better results than GP surrogates in small-sample regimes.
DAC

OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM

Yiqi Zhou, Yue Yuan, Yikai Wang, Bohao Liu, Qinxin Mei, Zhuohua Liu, Shan Shen, Wei Xing, Daying Sun, Li Li, and Guozhu Liu

In Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026

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An accuracy-constrained co-optimization framework for approximate digital computing-in-memory (DCiM) designs.
ICCAD

DIVE: Dynamic Information-Guided Variable Expansion for Deeper Analog Circuit Optimization

Zhuohua Liu, Weilun Xie, Yuxuan Zhang, Chen Wang, Yuanqi Hu, and Wei W. Xing

In 2025 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

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Proposed DIVE, a dynamic information-guided variable expansion framework that tackles the dimensionality challenge in analog circuit optimization, achieving up to 21.11x simulation reduction and 2.69x performance improvement.
ICCAD

ASTRA: Automatic Sizing of Transistors with Reasoning Agents

Wei W. Xing, Baowen Ou, Yuxuan Zhang, Zhuohua Liu, and Yuanqi Hu

In 2025 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

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Proposed ASTRA, an automatic transistor sizing framework leveraging LLM-based reasoning agents integrated with Bayesian Optimization for efficient analog circuit design.
ICCD

OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite

Shan Shen^*, Xingyang Li^*, Zhuohua Liu^*, Junhao Ma, Yikai Wang, Yiheng Wu, Yuquan Sun, and Wei W. Xing

In 2025 IEEE 43rd International Conference on Computer Design (ICCD), 2025

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Best Paper Candidate

Built a realistic SRAM yield analysis and optimization benchmark integrating parasitic-aware circuit generation and baseline evaluation frameworks.
DAC

KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology

Wei W. Xing, Weijian Fan, Zhuohua Liu, Yuan Yao, and Yuanqi Hu

In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

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Proposed an efficient and generalizable knowledge alignment and transfer framework for analog transistor sizing, reducing simulation cost by up to 50 percent and improving design performance by up to 20 percent.