CV
Ph.D. candidate at Beihang University. AI for EDA and analog circuit optimization.
Contact Information
| Name | Zhuohua Liu |
| Professional Title | Ph.D. Candidate in Integrated Circuits |
| zhuohualiu@buaa.edu.cn | |
| Phone | +86 178-8052-9108 |
| Location | , Beijing, Beijing |
Professional Summary
Ph.D. candidate at Beihang University specializing in AI for EDA, analog circuit optimization, and transistor sizing using Bayesian optimization and machine learning.
Education
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2025 - 2030 Beijing, China
Ph.D. Candidate
Beihang University
Integrated Circuits Science and Engineering
- School of Integrated Circuits Science and Engineering
- Expected graduation: 2030
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2021 - 2025 Shenzhen, China
Bachelor of Engineering
Shenzhen University
Mechanical, Electrical and Control Engineering
- Class Rank: Top 10%
- Weighted Average Score: 88.2 / 100
Awards
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2025 1st Prize, National Final — 2025 China Postgraduate IC Innovation Competition, EDA Elite Challenge Contest
China Postgraduate IC Innovation Competition
National first prize in the EDA Elite Challenge Contest.
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2024 National Scholarship
Ministry of Education of China
Awarded for outstanding academic performance.
Publications
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2025 ICCAD (CCF-B)
Proposed DIVE, achieving up to 21.11x simulation reduction and 2.69x performance improvement. (1st author)
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2024 DAC (CCF-A)
Efficient knowledge alignment and transfer framework for analog transistor sizing, reducing simulation cost by up to 50%. (Student 2nd author)
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2024 ICCD (CCF-B, Best Paper Candidate)
Realistic SRAM yield analysis and optimization benchmark with parasitic-aware circuit generation. (Co-1st author)
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2024 ISEDA (EI)
Framework enhancing Bayesian optimization for transistor sizing, reducing simulation cost by up to 50%. (1st author)